In recent years, there have been great advancements in the speed, power, and complexity of integrated circuits, such as application specific integrated circuit (ASIC) chips, random access memory (RAM) chips, microprocessor (uP) chips, and the like. These advancements have made possible the development of system-on-a-chip (SOC) devices. A SOC device integrates into a single chip all (or nearly all) of the components of a complex electronic system, such as a wireless receiver (i.e., cell phone, a television receiver, and the like). SOC devices greatly reduce the size, cost, and power consumption of the overall system.
Reductions in power consumption are particularly important in SOC devices. SOC devices are frequently used in portable devices that operate on battery power. Since maximizing battery life is a critical design objective in a portable device, it is essential to minimize the power consumption of SOC devices that may be used in the portable device. Furthermore, even if an SOC device is not used in a portable device, minimizing power consumption is still an important objective. The increased use of a wide variety of electronic products by consumers and businesses has caused corresponding increases in the electrical utility bills of homeowners and business operators. The increased use of electronic products also is a major contributor to the increased electrical demand that has caused highly publicized power shortages in the United States, particularly California.
To minimize power consumption in electronic devices, particularly SOC devices, many manufacturers have reduced the voltage levels at which electronic components operate. Low power integrated circuit (IC) technology operating at +3.3 volts replaced IC technology operating at +5.0 volts. The +3.3 volt IC technology was, in turn, replaced by +1.8 volt IC technology in many applications, particularly microprocessor and memory applications.
However, as the operating voltage of an integrated circuit is reduced, the noise margins of the integrated circuit are also reduced. Thus, an integrated circuit operating at +1.8 volts has smaller noise margins than a circuit operating at +3.3 volts. In deep submicron VLSI designs, two voltage sources for a chip design are common. One voltage source is an internal core power supply voltage (i.e., VDD) that has a lower swing voltage than the second voltage source, which provides the input/output (I/O) S pad ring voltage (i.e., VDDH). Common range values may include a VDD of 1-1.8 volts and a VDDH range of 2.3-3.6 volts.
Many processing systems implement states in which the output power supply, VDDH, is powered up while the internal core power supply, VDD, is zero. In order to allow circuits in the VDDH power supply domain to know the status of the VDD power supply domain, a power status signal in the VDD power supply domain is level shifted and latched into the higher VDDH power supply domain. The power status signal is a power-on reset (POR) signal that is detected and latched by the level shifting circuit. The POR signal indicates that the VDD power supply is ON.
Unfortunately, however, in many systems, if the VDD power supply is cycled ON and OFF several times, the latching circuit in the level shifter is not cleared. Thus, if the VDD power supply is turned OFF, the level shifter will falsely indicate that the VDD power supply is present. Some conventional level shifting circuits that clear the VDD status signal each time that VDD is turned OFF consume an excessive amount of current.
FIG. 4 illustrates conventional level shifter 400 according to one embodiment of the prior art. Level shifter 400 comprises N-channel transistors 402, 404, 405, 406 and 408, P-channel transistors 412-418, and capacitor 420. Level shifter 400 operates between VDDH=+3.3 volts and VSS=ground. The inputs to level shifter 400 are the VDD power supply and the IN signal. Level shifter generates the POWER VALID signal on the OUT node.
The IN signal indicates that the VDD power supply is enabled. When VDD goes high, the IN signal goes high shortly thereafter. When VDD goes low, the IN signal goes low shortly thereafter.
P-channel transistor 414 and N-channel transistor 404 form a first inverter stage. P-channel transistor 415 and N-channel transistor 406 form a second inverter stage. Finally, P-channel transistors 416, 417, and 418 and N-channel transistor 408 form a third inverter stage.
When the VDD power supply is on, VDD is a Logic 1 (+1.8 volts) and the IN signal also is a Logic 1 (+1.8 volts). When the IN signal goes to Logic 1, N-channel transistor 402 is on and the INT1* node is pulled down to ground (i.e., Logic 0). This turns on P-channel transistor 413. When the IN signal is Logic 1, N-channel transistor 404 is on and P-channel transistor 414 is off. This pulls the gate of N-channel transistor 405 to ground, thereby turning off N-channel transistor 405. Since P-channel transistor 413 is on and N-channel transistor 405 is off, the INT1 node is pulled up to the VDDH power supply rail. This ensures that P-channel transistor 412 is turned off. Thus the input stage latches the INT1 node to a Logic 1 level equal to VDDH and latches the INT1* node to Logic 0.
Since INT1 is VDDH, capacitor 420 charges up to VDDH. This turns on N-channel transistor 406 and turns off P-channel transistor 415, so that the INT2 node is pulled low (i.e., Logic 0). The Logic 0 on INT2 node turns on P-channel transistors 416, 417 and 418 and turns off N-channel transistor 408. This drives the OUT node high, so that POWER VALID is Logic 1.
At some point, the VDD power supply may turn off, so that the VDD power supply rail at the source of P-channel transistor 414 goes to Logic 0 (i.e., ground). The IN signal goes to Logic 0 a fraction of a second after VDD turns off. Unfortunately, the Logic 0 value of the IN signal does not propagate through the first inverter formed by P-channel transistor 414 and N-channel transistor 404. This is because the VDD power supply rail provides power to the first inverter, and VDD has turned off.
As a result, when the IN signal goes to Logic 0, the gate of N-channel transistor 405 does not go to Logic 1. Since N-channel transistor 405 is stuck in the off position, the INT1 node is stuck at Logic 1. Therefore, if the VDD power supply is cycled on and off, the INT1 node in the latching circuit in level shifter 400 is not cleared and the OUT signal is stuck at Logic 1. Thus, if the VDD power supply is turned off, level shifter 400 falsely indicates that the VDD power supply is still present.
Therefore, there is a need in the art for integrated circuits in which one power supply domain be powered up while internal core circuitry is not powered up. More particularly, there is a need for an improved level shifter circuit that indicates the presence of a valid VDD power supply to a higher VDDH power supply domain that clears itself whenever the VDD power supply signal is turned OFF.